1. Field of the Invention
This invention relates to direct memory access (DMA) bus arbitration. More particularly, it relates to a technique for achieving more efficient bus usage by performing arbitration for the next transfer during the current transfer.
2. Description of the Prior Art
The prior art contains many attempts to maximize bus usage and improve performance during DMA transfers. IBM Technical Disclosure Bulletin, Vol. 30, No. 12, May, 1988, Page 211 describes a technique in which a DMA arbitration results in a larger data transfer to reduce the total amount of arbitrations that must occur to pass a given data block. IBM Technical Disclosure Bulletin, Vol. 24, No. 10, March, 1982, Page 5295 discloses an arrangement which provides for an automatic channel request in order to reduce data store size requirements and the amount of microcode for performing a DMA transfer.
Commonly assigned U.S. application Ser. No. 176,122, filed Mar. 31, 1988 now U.S. Pat. No. 4,912,632 relates to a memory subsystem controller including means for causing a memory transfer initiated by the DMA to be interrupted at a cache line boundary to service a processor request and thereafter resume data transfer.
Concurrently filed, commonly assigned U.S. application Ser. No. 07/297,778, herewith incorporated by reference, relates to a DMA controller requiring no intervention from a main processor once the first of a series of block transfers has begun.
Typically in the prior art one DMA data transfer is completed before another bus arbitration occurs. Not only does bus arbitration consume overhead in prior art systems, which in itself is undesirable, there may be sufficient idle time on the bus for a request from some other device to be granted before the next DMA bus request is raised, thereby delaying the grant which would allow another DMA data transfer to commence.
It is desirable to minimize idle time on the bus and to minimize the time between DMA arbitration initiations necessary to transfer large amounts of data. In the prior art there is no teaching, however, of optimizing bus bandwidth by initiating a bus request for an ensuing transfer while a current transfer is still in progress, thereby enabling back to back DMA transfers.